View ATTINY13-10SU_8967659.PDF datasheet online --- IC-ON-LINE

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features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 120 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 20 mips througput at 20 mhz ? high endurance non-volatile memory segments ? 1k bytes of in-system self-programmable flash program memory ? 64 bytes eeprom ? 64 bytes internal sram ? write/erase cyles: 10,000 flash/100,000 eeprom ? data retention: 20 years at 85c/100 years at 25c (see page 6 ) ? programming lock for self-programming flash & eeprom data security ? peripheral features ? one 8-bit timer/counter with prescaler and two pwm channels ? 4-channel, 10-bit adc with internal voltage reference ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? special microcontroller features ? debugwire on-chip debug system ? in-system programmable via spi port ? external and internal interrupt sources ? low power idle, adc noise reduction, and power-down modes ? enhanced power-on reset circuit ? programmable brown-out detection circuit ? internal calibrated oscillator ? i/o and packages ? 8-pin pdip/soic: six programmable i/o lines ? 20-pad mlf: six programmable i/o lines ? operating voltage: ? 1.8 - 5.5v for attiny13v ? 2.7 - 5.5v for attiny13 ? speed grade ? attiny13v: 0 - 4 mhz @ 1.8 - 5.5v, 0 - 10 mhz @ 2.7 - 5.5v ? attiny13: 0 - 10 mhz @ 2.7 - 5.5v, 0 - 20 mhz @ 4.5 - 5.5v ? industrial temperature range ? low power consumption ? active mode: ? 1 mhz, 1.8v: 240a ? power-down mode: ? < 0.1a at 1.8v 8-bit microcontroller with 1k bytes in-system programmable flash attiny13 attiny13v summary not recommended for new designs. use attiny13a. rev. 2535is?avr?05/08
2 2535is?avr?05/08 attiny13 1. pin configurations figure 1-1. pinout attiny13/attiny13v 1 2 3 4 8 7 6 5 (pcint5/reset/adc0/dw) pb5 (pcint3/clki/adc3) pb3 (pcint4/adc2) pb4 gnd vcc pb2 (sck/adc1/t0/pcint2) pb1 (miso/ain1/oc0b/int0/pcint1) pb0 (mosi/ain0/oc0a/pcint0) 8-pdip/soic 1 2 3 4 5 20-qfn/mlf 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 (pcint5/reset/adc0/dw) pb5 (pcint3/clki/adc3) pb3 dnc dnc (pcint4/adc2) pb4 dnc dnc gnd dnc dnc vcc pb2 (sck/adc1/t0/pcint2) dnc pb1 (miso/ain1/oc0b/int0/pcint1) pb0 (mosi/ain0/oc0a/pcint0) dnc dnc dnc dnc dnc note: bottom pad should be soldered to ground. dnc: do not connect 1 2 3 4 5 10-qfn/mlf 10 9 8 7 6 (pcint5/reset/adc0/dw) pb5 (pcint3/clki/adc3) pb3 dnc (pcint4/adc2) pb4 gnd vcc pb2 (sck/adc1/t0/pcint2) dnc pb1 (miso/ain1/oc0b/int0/pcint1) pb0 (mosi/ain0/oc0a/pcint0) note: bottom pad should be soldered to ground. dnc: do not connect
3 2535is?avr?05/08 attiny13 1.1 pin descriptions 1.1.1 vcc digital supply voltage. 1.1.2 gnd ground. 1.1.3 port b (pb5:pb0) port b is a 6-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the attiny13 as listed on page 54 . 1.1.4 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 18-1 on page 115 . shorter pulses are not guaranteed to generate a reset. the reset pin can also be used as a (weak) i/o pin.
4 2535is?avr?05/08 attiny13 2. overview the attiny13 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerf ul instructions in a single cl ock cycle, the attiny13 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 block diagram figure 2-1. block diagram program counter internal o s cilla tor watchdog timer s tack pointer program fla s h s ram mcu control regi s ter general purpo s e regi s ter s in s truction regi s ter timer/ counter0 in s truction decoder data dir. reg.port b data regi s ter port b programming logic timing and control mcu s tatu s regi s ter s tatu s regi s ter alu port b driver s pb0-pb5 vcc gnd control line s 8 -bit databu s z adc / analog comparator interrupt unit calibrated y x re s et clki watchdog o s cillator data eeprom
5 2535is?avr?05/08 attiny13 the avr core combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. the attiny13 provides the following features: 1k byte of in-system programmable flash, 64 bytes eeprom, 64 bytes sram, 6 ge neral purpose i/o lines, 32 general purpose working reg- isters, one 8-bit timer/counter with compare modes, internal and external interrupts, a 4- channel, 10-bit adc, a programm able watchdog timer wit h internal oscillato r, and three soft- ware selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counter, adc, analog comparator, and interrupt system to continue functioning. the power-down mode saves the register contents, di sabling all chip functions until the next inter- rupt or hardware reset. the adc noise reduction mode stops the cpu and all i/o modules except adc, to minimize switch ing noise during adc conversions. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be re-programmed in-system through an spi serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the avr core. the attiny13 avr is supported with a full su ite of program and system development tools including: c compilers, macro assemblers, program debugger/si mulators, and evaluation kits.
6 2535is?avr?05/08 attiny13 3. about 3.1 resources a comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. 3.3 data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25 c.
7 2535is?avr?05/08 attiny13 4. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f sreg i t h s v n z c page 9 0x3e reserved ? ? ? ? ? ? ? ? 0x3d spl sp[7:0] page 11 0x3c reserved ? 0x3b gimsk ? int0 pcie ? ? ? ? ? page 46 0x3a gifr ? intf0 pcif ? ? ? ? ? page 47 0x39 timsk0 ? ? ? ? ocie0b ocie0a toie0 ? page 74 0x38 tifr0 ? ? ? ? ocf0b ocf0a tov0 ? page 75 0x37 spmcsr ? ? ? ctpb rflb pgwrt pgers self- page 97 0x36 ocr0a timer/counter ? output compare register a page 74 0x35 mcucr ?pudsesm1sm0 ?isc01isc00 page 32 0x34 mcusr ? ? ? ? wdrf borf extrf porf page 41 0x33 tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 page 72 0x32 tcnt0 timer/counter (8-bit) page 73 0x31 osccal oscillator calibration register page 27 0x30 reserved ? 0x2f tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 page 69 0x2e dwdr dwdr[7:0] page 96 0x2d reserved ? 0x2c reserved ? 0x2b reserved ? 0x2a reserved ? 0x29 ocr0b timer/counter ? output compare register b page 74 0x28 gtccr tsm ? ? ? ? ? ? psr10 page 77 0x27 reserved ? 0x26 clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 page 28 0x25 reserved ? 0x24 reserved ? 0x23 reserved ? 0x22 reserved ? 0x21 wdtcr wdtif wdtie wdp3 wdce wde wdp2 wdp1 wdp0 page 41 0x20 reserved ? 0x1f reserved ? 0x1e eearl ? ? eeprom address register page 20 0x1d eedr eeprom data register page 20 0x1c eecr ? ? eepm1 eepm0 eerie eempe eepe eere page 21 0x1b reserved ? 0x1a reserved ? 0x19 reserved ? 0x18 portb ? ? portb5 portb4 portb3 portb2 portb1 portb0 page 56 0x17 ddrb ? ? ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 56 0x16 pinb ? ? pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 57 0x15 pcmsk ? ? pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 page 47 0x14 didr0 ? ? adc0d adc2d adc3d adc1d ain1d ain0d page 80 , page 94 0x13 reserved ? 0x12 reserved ? 0x11 reserved ? 0x10 reserved ? 0x0f reserved ? 0x0e reserved ? 0x0d reserved ? 0x0c reserved ? 0x0b reserved ? 0x0a reserved ? 0x09 reserved ? 0x08 acsr acd acbg aco aci acie ? acis1 acis0 page 79 0x07 admux ? refs0 adlar ? ? ? mux1 mux0 page 91 0x06 adcsra aden adsc adate adif adie adps2 adps1 adps0 page 92 0x05 adch adc data register high byte page 93 0x04 adcl adc data register low byte page 93 0x03 adcsrb ?acme ? ? ? adts2 adts1 adts0 page 94 0x02 reserved ? 0x01 reserved ? 0x00 reserved ?
8 2535is?avr?05/08 attiny13 notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory address es should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by usin g the sbis and sbic instructions.ome of the status flags are cleared by writing a logical one to them. note that, unlike mo st other avrs, the cbi and sbi instructions will only operation the specified bit, and can therefore be used on registers contai ning such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only.
9 2535is?avr?05/08 attiny13 5. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in regi ster is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1
10 2535is?avr?05/08 attiny13 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
11 2535is?avr?05/08 attiny13 6. ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging alternative, complies to the european direc tive for restriction of hazardous substances (rohs direc- tive). also halide free and fully green 3. for speed vs. v cc , see ?speed grades? on page 117 . speed (mhz) (3) power supply ordering code (2) package (1) operation range 10 1.8 - 5.5 attiny13v-10pu attiny13v-10su attiny13v-10ssu attiny13v-10mu attiny13v-10mmu 8p3 8s2 s8s1 20m1 10m1 industrial (-40 c to 85 c) 20 2.7 - 5.5 attiny13-20pu attiny13-20su attiny13-20ssu attiny13-20mu attiny13-20mmu 8p3 8s2 s8s1 20m1 10m1 industrial (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s2 8-lead, 0.209" wide, plastic small outline package (eiaj soic) s8s1 8-lead, 0.150" wide, plastic gull-wing small outline (jedec soic) 20m1 20-pad, 4 x 4 x 0.8 mm body, lead pitch 0. 50 mm, micro lead frame package (mlf) 10m1 10-pad, 3 x 3 x 1 mm body, lead pitch 0.50 mm, micro lead frame package (mlf)
12 2535is?avr?05/08 attiny13 7. packaging information 7.1 8p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
13 2535is?avr?05/08 attiny13 7.2 8s2 title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 8s2 stn f 8s2, 8-lead, 0.208? body, plastic small outline package (eiaj) 4/15/08 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs aren't included. 3. determines the true geometric position. 4. values b,c apply to plated terminal. the standard thickness of the plating layer shall measure between 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 4 c 0.15 0.35 4 d 5.13 5.35 e1 5.18 5.40 2 e 7.70 8.26 l 0.51 0.85 0 8 e 1.27 bsc 3 1 1 n n e e top view t o p v i e w c c e1 e 1 end view e n d v i e w a a b b l l a1 a 1 e e d d side view s i d e v i e w
14 2535is?avr?05/08 attiny13 7.3 s8s1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. note: 10/10/01 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 a h 1 2 n 3 top view c e end view a b l a2 e d side view common dimensions (unit of measure = mm) symbol min nom max note this drawing is for general information only. refer to jedec drawing ms-012 for proper dimensions, tolerances, datums, etc. a ? ? 1.75 b ? ? 0.51 c ? ? 0.25 d ? ? 5.00 e ? ? 4.00 e 1.27 bsc h ? ? 6.20 l ? ? 1.27
15 2535is?avr?05/08 attiny13 7.4 20m1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20m1 , 20-pad, 4 x 4 x 0.8 mm body, lead pitch 0.50 mm, a 20m1 10/27/04 2.6 mm exposed pad, micro lead frame package (mlf) a 0.70 0.75 0.80 a1 ? 0.01 0.05 a2 0.20 ref b 0.18 0.23 0.30 d 4.00 bsc d2 2.45 2.60 2.75 e 4.00 bsc e2 2.45 2.60 2.75 e 0.50 bsc l 0.35 0.40 0.55 side view pin 1 id pin #1 notch (0.20 r) bottom view top view note: reference jedec standard mo-220, fig . 1 (saw singulation) wggd-5. common dimensions (unit of measure = mm) symbol min nom max note d e e a2 a1 a d2 e2 0.08 c l 1 2 3 b 1 2 3
16 2535is?avr?05/08 attiny13 7.5 10m1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 10m1, 10-pad, 3 x 3 x 1.0 mm body, lead pitch 0.50 mm, 1.64 x 2.60 mm exposed pad, micro lead frame package a 10m1 7/7/06 common dimensions (unit of measure = mm) symbol min nom max note a 0.80 0.90 1.00 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 2.90 3.00 3.10 d1 1.40 ? 1.75 e 2.90 3.00 3.10 e1 2.20 ? 2.70 e 0.50 l 0.30 ? 0.50 y ? ? 0.08 k 0.20 ? ? pin 1 id top view d e a1 a side view bottom view d1 e1 l b e k 1 2 notes: 1. this package conforms to jedec reference mo-229c, variation veed-5. 2. the terminal #1 id is a lasser-marked feature. y
17 2535is?avr?05/08 attiny13 8. errata the revision letter in this section refers to the revision of the attiny13 device. 8.1 attiny13 rev. d ? eeprom can not be written below 1.9 volt 1. eeprom can not be written below 1.9 volt writing the eeprom at v cc below 1.9 volts might fail. problem fix/workaround do not write the eeprom when v cc is below 1.9 volts. 8.2 attiny13 rev. c revision c has not been sampled. 8.3 attiny13 rev. b ? wrong values read after erase only operation ? high voltage serial prog ramming flash, eeprom, fuse and lock bits may fail ? device may lock for further programming ? debugwire communication not blocked by lock-bits ? watchdog timer interrupt disabled ? eeprom can not be written below 1.9 volt 8.3.1 wrong values read after erase only operation at supply voltages below 2.7 v, an eeprom location that is er ased by the er ase only oper- ation may read as programmed (0x00). problem fix/workaround if it is necessary to read an eeprom location after erase only, use an atomic write opera- tion with 0xff as data in order to erase a location. in any case, the write only operation can be used as intended. thus no s pecial considerations are needed as long as the erased loca- tion is not read before it is programmed. 8.3.2 high voltage serial programming fl ash, eeprom, fuse and lock bits may fail writing to any of these locations and bits may in some occasions fail. problem fix/workaround after a writing has been initiated, always observe the rdy/bsy signal. if the writing should fail, rewrite until the rdy/bsy verifies a correct writing. this will be fixed in revision d. 8.3.3 device may lock for further programming special combinations of fuse bits will lock the device for further programming effectively turning it into an ot p device. the following combinations of settings/fuse bits will cause this effect: ? 128 khz internal oscilla tor (cksel[1..0] = 11), sh ortest start-up time (sut[1..0] = 00), debugwire enabled (dwen = 0) or reset disabled rstdisbl = 0. ? 9.6 mhz internal oscillator (cksel[1.. 0] = 10), shortest start-up time (sut[1..0] = 00), debugwire enabled (dwen = 0) or reset disabled rstdisbl = 0.
18 2535is?avr?05/08 attiny13 ? 4.8 mhz internal oscillator (cksel[1.. 0] = 01), shortest start-up time (sut[1..0] = 00), debugwire enabled (dwen = 0) or reset disabled rstdisbl = 0. problem fix/ workaround avoid the above fuse combinatio ns. selecting longer start-up time will eliminate the problem. 8.3.4 debugwire communication not blocked by lock-bits when debugwire on-chip debug is enabled (dwen = 0), the contents of program memory and eeprom data memory can be read even if the lock-bit s are set to bloc k further reading of the device. problem fix/ workaround do not ship products with on-chip debug of the tiny13 enabled. 8.3.5 watchdog timer interrupt disabled if the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared . this is only applicable in interrupt only mode. if the watchdog is configured to reset the device in the watchdog time- out following an interrupt, the device works correctly. problem fix / workaround make sure there is enough time to always service the first timeout event before a new watchdog timeout occurs. this is done by selecting a long enough time-out period. 8.3.6 eeprom can not be written below 1.9 volt writing the eeprom at v cc below 1.9 volts might fail. problem fix/workaround do not write the eeprom when v cc is below 1.9 volts. 8.4 attiny13 rev. a revision a has not been sampled.
19 2535is?avr?05/08 attiny13 9. datasheet revision history please note that page numbers in this section are referring to this document. 9.1 rev. 2535i-05/08 1. updated document template, layout and paragraph formats. 2. updated ?features? on page 1 . 3. created sections: ? ?calibrated internal rc osc illator accuracy ? on page 118 ? ?analog comparator characteristics? on page 119 4. updated sections: ? ?system clock and clock options? on page 23 ? ?calibrated internal 4.8/9.6 mhz oscilla tor? on page 25 ? ?external interrupts? on page 45 ? ?analog noise canceling techniques? on page 88 ? ?limitations of debugwire? on page 96 ? ?reading fuse and lock bits from firmware? on page 99 ? ?fuse bytes? on page 103 ? ?calibration bytes? on page 104 ? ?high-voltage serial programming? on page 108 ? ?ordering information? on page 11 5. updated figure: ? ?analog input circuitry? on page 87 ? ?high-voltage serial programming timing? on page 122 6. moved figures: ? ?serial programming timing? on page 121 ? ?serial programming waveform? on page 121 ? ?high-voltage serial programming timing? on page 122 7. updated tables: ? ?dc characteristics, ta = -40c to 85c? on page 115 ? ?serial programming characteristics, ta = -40c to 85c, vcc = 1.8 - 5.5v (unless otherwise noted)? on page 121 8. moved tables: ? ?serial programming instruction set? on page 107 ? ?serial programming characteristics, ta = -40c to 85c, vcc = 1.8 - 5.5v (unless otherwise noted)? on page 121 ? ?high-voltage serial programming characteristics ta = 25c, vcc = 5.0v 10% (unless otherwise noted)? on page 122 9. updated register description for sections: ? ?tccr0a ? timer/counter control register a? on page 69 ? ?didr0 ? digital input disable register 0? on page 94 10. updated description in step 1. on page 106 . 11. changed device status to ?not recommended for new designs?.
20 2535is?avr?05/08 attiny13 9.2 rev. 2535h-10/07 9.3 rev. 2535g-01/07 9.4 rev. 2535f-04/06 9.5 rev. 2535e-10/04 1. updated ?features? on page 1 . 2. updated ?pin configurations? on page 2 . 3. added ?data retention? on page 6 . 4. updated ?assembly code example(1)? on page 39 . 5. updated table 21 in ?alternate functions of port b? on page 54 . 6. updated bit 5 description in ?gimsk ? general interrupt mask register? on page 46 . 7. updated ?adc voltage reference? on page 87 . 8. updated ?calibration bytes? on page 104 . 9. updated ?read calibration byte? on page 108 . 10. updated table 51 in ?serial programming charac teristics? on page 121 . 11. updated algorithm in ?high-voltage serial programming algorithm? on page 109 . 12. updated ?read calibration byte? on page 112 . 13. updated values in ?external clock drive? on page 118 . 14. updated ?ordering information? on page 11 . 15. updated ?packaging information? on page 12 . 1. removed preliminary. 2. updated table 7-1 on page 30 , table 8-1 on page 42 , table 18-8 on page 121 . 3. removed note from table 7-1 on page 30 . 4. updated ?bit 6 ? acbg: analog comparator bandgap select? on page 79 . 5. updated ?prescaling and conversion timing? on page 83 . 6. updated figure 18-4 on page 121 . 7. updated ?dc characteristics? on page 115 . 8. updated ?ordering information? on page 11 . 9. updated ?packaging information? on page 12 . 1. revision not published. 1. bits eemwe/eewe changed to eempe/eepe in document. 2. updated ?pinout attiny13/attiny13v? on page 2 . 3. updated ?write fuse low bits? in table 17-13 on page 110 , table 18-3 on page 118 . 2. added ?pin change interrupt timing? on page 45 . 4. updated ?gimsk ? general interrupt mask register? on page 46 . 5. updated ?pcmsk ? pin change mask register? on page 47 . 6. updated item 4 in ?serial programming algorithm? on page 106 . 7. updated ?high-voltage serial programming algorithm? on page 109 . 8. updated ?dc characteristics? on page 115 . 9. updated ?typical characteristics? on page 122 . 10. updated ?ordering information? on page 11 . 11. updated ?packaging information? on page 12 . 12. updated ?errata? on page 17 .
21 2535is?avr?05/08 attiny13 9.6 rev. 2535d-04/04 9.7 2535c-02/04 9.8 rev. 2535b-01/04 9.9 rev. 2535a-06/03 1. maximum speed grades changed - 12mhz to 10mhz - 24mhz to 20mhz 2. updated ?serial programming instruction set? on page 107 . 3. updated ?speed grades? on page 117 4. updated ?ordering information? on page 11 1. c-code examples updated to use legal iar syntax. 2. replaced occurrences of wdif with wdtif and wdie with wdtie. 3. updated ?stack pointer? on page 11 . 4. updated ?calibrated internal 4.8/9. 6 mhz oscillator? on page 25 . 5. updated ?osccal ? oscillator calibrati on register? on page 27 . 6. updated typo in introduction on ?watchdog timer? on page 37 . 7. updated ?adc conversion time? on page 86 . 8. updated ?serial programming? on page 105 . 9. updated ?electrical characteristics? on page 115 . 10. updated ?ordering information? on page 11 . 11. removed rev. c from ?errata? on page 17 . 1. updated figure 2-1 on page 4 . 2. updated table 7-1 on page 30 , table 8-1 on page 42 , table 14-2 on page 91 and table 18-3 on page 118 . 3. updated ?calibrated internal 4.8/9. 6 mhz oscillator? on page 25 . 4. updated the whole ?watchdog timer? on page 37 . 5. updated figure 17-1 on page 105 and figure 17-2 on page 108 . 6. updated registers ?mcucr ? mcu control register? on page 56 , ?tccr0b ? timer/counter control register b? on page 72 and ?didr0 ? digital input disable reg- ister 0? on page 80 . 7. updated absolute maximum rati ngs and dc characteristics in ?electrical characteris- tics? on page 115 . 8. added ?speed grades? on page 117 9. updated ?? on page 120 . 10. updated ?typical characteristics? on page 123 . 11. updated ?ordering information? on page 11 . 12. updated ?packaging information? on page 12 . 13. updated ?errata? on page 17 . 14. changed instances of eear to eearl. 1. initial revision.
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